About

Transistors to
Tapeout.

I'm an aspiring RTL and Physical Design Engineer with hands-on experience building complete hardware design flows — from custom CMOS logic cells through arithmetic datapath construction, FSM arbitration, layout, and physical verification.

My work lives at the intersection of theory and silicon: designing circuits that are not only functionally correct but physically realizable, with measurable power, area, and delay targets.

I'm drawn to the rigor of hardware design — where every transistor placement and timing path has real consequence.

Design & Verification

Verilog / RTL ASIC Datapath FSM Design DFF / Sequential Logic

Physical Design

CMOS Layout DRC / LVS Cadence Virtuoso Extracted Simulation

Analysis

Power Analysis Delay Estimation Area Optimization Waveform Verification

Focus Area

RTL & Physical Design

Arithmetic datapaths, control logic, CMOS layout, and physical verification.

Tools & Software

Cadence Virtuoso · Spectre Simulator · HSPICE · Calibre DRC/LVS · Design Compiler

Education

Electrical & Computer Engineering
VLSI Design · Digital Systems · CMOS IC Design

Currently Seeking

RTL Design Engineer · Physical Design Engineer · ASIC Design roles

Projects

Hardware Design Work

Full-stack hardware projects from CMOS transistor level through verified silicon layout.

VLSI · CMOS · ASIC

Custom Arithmetic Datapath for ASIC-Style Compute Systems

Built a multiplier/divider compute block with FSM arbitration, DFF sequencing, custom CMOS layout, and DRC/LVS verification.

1.6 ns delay 31.63 µW power 0.00141 mm² area DRC/LVS ✓

Mallika's Focus
Half Subtractor · Full Subtractor · HS_MUX · Layout Verification · Performance Metrics

ASIC Datapath FSM Control CMOS Layout DRC/LVS Power-Area-Delay

CMOS · Logic Design · Arithmetic

CMOS Logic Cell Design for Arithmetic Circuits

Designed, simulated, laid out, and verified CMOS XOR, full-adder, and 4-bit ripple-carry-adder circuits with waveform validation, delay measurement, DRC, and LVS.

XOR · FA · 4-bit RCA Delay Measured DRC/LVS ✓

Mallika's Focus
CMOS XOR · Full Adder · Ripple-Carry Adder · Delay Measurement · DRC/LVS Verification

CMOS Design Arithmetic Circuits Delay Analysis Layout DRC/LVS Cadence

Digital VLSI · Optimization · Encoder

Priority Encoder Optimization for High-Speed Digital Logic

Designed, optimized, laid out, and verified PE4, MUX4, and PE16 circuits through critical-path analysis, logic-level reduction, floorplanning, and extracted-layout timing validation.

707 ps → 24.5 ps PE16 Optimized DRC/LVS ✓

Mallika's Focus
Priority Encoder · MUX Design · Critical Path Optimization · Floorplanning · Extracted Layout Verification

Digital VLSI Priority Encoder MUX Design Critical Path Floorplanning DRC/LVS

VLSI Design · ASIC · CMOS · Physical Verification

Custom MOS VLSI Arithmetic Processing Unit

Multiplier + divider datapath with arbiter FSM, DFF registers, layout, DRC/LVS, and performance validation.

This project implemented a complete MOS VLSI arithmetic processing unit that selects between multiplication and division operations using arbiter-controlled logic, registers the inputs and outputs through D flip-flops, and validates the final design through layout, DRC/LVS, waveform verification, and extracted performance metrics.

Results Snapshot

Area

0.00141

mm²

Delay

1.6

Power

31.63

µW

Validation

DRC Passed
LVS Passed

+ Waveforms

Contribution

Mallika's Focus

Components Owned

Half Subtractor · Full Subtractor · HS_MUX · Layout Verification · Performance Metrics

Mallika's contribution focused on the divider-side arithmetic path and final validation work. Her work connected subtractor logic, MUX-based restore behavior, layout verification, and final performance analysis — tying the divider subsystem from schematic design through to verified silicon layout and extracted metrics.

Half Subtractor Divider-side subtractor logic used for compare/subtract behavior in the restoring division algorithm.

Full Subtractor Borrow-aware subtractor block used in the restoring division datapath for multi-bit subtraction.

HS_MUX MUX-based restore logic used to select between the original and subtracted values in the division step.

Design Flow

From Cells to Verified Silicon

CMOS Cells

The project began with custom CMOS logic cells, including full adders, half subtractors, full subtractors, and MUX structures designed at transistor level.

Multiplier / Divider Datapath

The arithmetic datapath combined a 4-bit multiplier using partial product accumulation and a 4-bit restoring divider with subtractor/MUX logic.

Arbiter FSM

An arbiter FSM selected between multiplication and division requests and generated stall behavior when no valid operation was requested by the system.

Layout Verification

The design was physically implemented in Cadence Virtuoso and verified through DRC, LVS, and waveform simulation using extracted parasitics.

Final Performance Metrics

The final design was evaluated using extracted area, delay, and power results — confirming 1.6 ns delay, 31.63 µW power, and 0.00141103 mm² area.

Evidence Gallery

Design Documentation

Full system architecture with DFF, FSM, multiplier, and divider blocks.

Datapath overview showing compute path routing and MUX arbitration.

Arbiter FSM showing MUL, DIV, and STALL state transitions.

Custom CMOS full adder used in the multiplier partial product tree.

Half subtractor for the first stage of restoring division compare logic.

Borrow-propagating full subtractor for multi-bit division steps.

MUX select logic restoring original remainder when subtraction underflows.

Arbiter request/grant logic with stall generation and priority encoding.

Top-level system schematic showing all blocks connected with DFFs.

Verifies MUL/DIV select and stall behavior across all input combinations.

Difference and borrow outputs verified across all 4 input states.

Verifies borrow-in propagation and 3-input subtraction correctness.

Confirms correct restore behavior based on borrow output selection.

End-to-end simulation verifying multiply and divide outputs through DFF registers.

Transistor-level CMOS layout of the half subtractor cell.

Physical implementation of the full subtractor with borrow routing.

Layout of the restore MUX with select signal routing.

Complete 4-bit restoring divider physical layout with all cells placed.

Physical layout of the FSM arbiter logic block.

Top-level layout of the complete arithmetic processing unit — 0.00141103 mm².

DRC Passed LVS Passed

DRC Passed LVS Passed — Full system clean.

Minimum timing — 1.7 ns extracted measurement.

Minimum timing — 1.8 ns extracted measurement.

Area estimation — extracted layout measurement.

Final performance metrics — PAD summary table.

Metric	Value	Unit	Notes
Total Area	0.00141103	mm²	Extracted from layout
Propagation Delay	1.6	ns	Worst-case extracted path
Power Dissipation	31.63	µW	Dynamic + static, extracted sim
DRC Status	Passed	—	0 violations, Calibre
LVS Status	Passed	—	Schematic vs. layout matched
PAD	Verified	—	All three metrics within targets

Final Outcome

Project Summary

This project connected transistor-level CMOS design, arithmetic datapath construction, FSM control, sequential logic, physical layout, and verification into one complete hardware design flow. The final result was a custom arithmetic processing unit validated through waveform simulation, DRC/LVS checks, and extracted performance metrics — demonstrating a full path from CMOS cells to verified silicon layout with measurable power, area, and delay results.

CMOS Design · Arithmetic Circuits · Delay Analysis · DRC/LVS · Cadence

CMOS Logic Cell Design for Arithmetic Circuits

XOR, full-adder, and 4-bit ripple-carry-adder design with schematic simulation, layout, DRC/LVS verification, waveform validation, and delay analysis.

This project built Mallika's foundation in custom CMOS digital design. It started with XOR gate implementation, then expanded into full-adder design and 4-bit ripple-carry-adder construction, with validation through functional waveforms, delay measurements, layout, DRC, and LVS.

Results Snapshot

Logic Built

XOR · FA
4-bit RCA

3 circuits end-to-end

Timing Proof

Cout / Sum
Delay Measured

Rise + fall, schematic & layout

Physical Verification

DRC Passed
LVS Passed

All 3 cells verified

Validation

Schematics
Waveforms
Layout

Complete design evidence

Contribution

Mallika's Focus

Components Owned

CMOS XOR · Full Adder · Ripple-Carry Adder · Delay Measurement · Layout Verification

Mallika's work demonstrated the full custom digital circuit design flow: schematic construction, functional waveform validation, DUT-based delay measurement, layout implementation, and DRC/LVS verification — establishing the cell-level foundation later used in larger arithmetic datapaths.

XOR Gate

XOR Gate Custom CMOS gate verified through schematic simulation, layout, DRC, and LVS.

1-bit Full Adder Arithmetic cell optimized and measured for Sum and Cout rising/falling delay.

4-bit Ripple-Carry Adder Multi-bit arithmetic circuit built from full-adder logic and validated through S0–S3, C4 output waveforms.

Design Flow

XOR Gate to Verified 4-bit Adder

XOR Gate

Started with CMOS XOR design — schematic construction, functional simulation, waveform validation, power measurement, layout, DRC, and LVS verification.

Full Adder

Built a 1-bit full adder and evaluated Sum and Cout behavior through functional waveform simulation at schematic level.

DUT Delay Testing

Used DUT structures to measure rising and falling delays for Sum and Cout outputs at both schematic and extracted layout levels.

4-bit Ripple-Carry Adder

Scaled the single-bit adder into a 4-bit RCA and verified output behavior across all sum bits S0, S1, S2, S3 and carry-out C4.

Layout Verification

Completed physical layout for XOR, full adder, and 4-bit RCA. Verified all designs through DRC and LVS checks with zero violations.

Evidence Gallery

Design Documentation

Custom CMOS XOR schematic with transistor-level implementation.

Functional simulation waveform showing correct XOR truth table outputs.

Testbench setup used to drive all 4 input combinations.

Average and dynamic power measured from simulation results.

Transistor-level CMOS layout of the XOR gate cell.

1-bit full adder CMOS schematic showing Sum and Cout logic paths.

Waveform confirming correct Sum and Cout outputs across all input states.

Physical layout of the 1-bit full adder cell.

DUT testbench schematic used to drive the delay measurement setup.

Rising edge delay measurement for Cout output path.

Falling edge delay measurement for Cout output path.

Rising edge delay measurement for Sum output path.

Falling edge delay measurement for Sum output path.

Extracted layout delay results showing parasitics impact on timing.

DUT-based measurement infrastructure for systematic delay capture.

Top-level 4-bit ripple-carry adder schematic with 4 cascaded full adders.

Output waveform showing S0, S1, S2, S3 and C4 for multiple input combinations.

Worst-case ripple scenario demonstrating maximum carry propagation delay.

Measured delay for the MSB sum and final carry-out bits.

Transistor-level physical layout of the custom CMOS XOR gate.

1-bit full adder layout with routing for Sum, Cout, and all inputs.

Complete 4-bit ripple-carry adder physical layout with all cells placed and routed.

DRC Passed LVS Passed

DRC Passed LVS Passed — All 3 cells clean.

Final Outcome

Project Summary

This project established Mallika's foundation in custom CMOS digital design by connecting schematic-level logic design, waveform validation, delay measurement, physical layout, and DRC/LVS verification. It served as the technical base for larger arithmetic datapath projects involving multipliers, dividers, FSM control, and full-system layout verification — demonstrating the complete cell-level design flow from transistor schematic to verified silicon layout.

Digital VLSI · Priority Encoder · Critical Path · Floorplanning · DRC/LVS

Priority Encoder Optimization for High-Speed Digital Logic

PE4, MUX4, and PE16 design optimization with critical-path analysis, reduced logic depth, floorplanning, extracted layout simulation, DRC/LVS, and timing validation.

This project focused on structured digital circuit optimization. Mallika designed and tested PE4 and MUX structures, scaled them into a PE16 priority encoder, identified worst-case delay paths, optimized logic structure to reduce delay, and then implemented PE4, MUX4, and PE16 layouts with DRC/LVS and extracted-layout timing validation.

Results Snapshot

Optimized PE16 Delay

23.262 ps rise
24.511 ps fall

After logic-level reduction

Original PE16 Delay

707.458 ps

Falling — before optimization

Extracted Layout Proof

PE4 · MUX4
PE16

All 3 blocks verified

Validation

DRC Passed
LVS Passed

+ Extracted waveforms

Contribution

Mallika's Focus

Components Owned

PE4 Design · 4:1 MUX Design · PE16 Scaling · Critical Path Optimization · Floorplanning · Extracted Layout Timing

Mallika's work demonstrated a performance-driven VLSI design flow: starting from schematic-level PE4 and MUX structures, scaling into a PE16 priority encoder, identifying the worst-case critical path, modifying the logic structure to reduce delay from 707 ps to 24.5 ps, and validating the final layouts through extracted simulation, DRC, and LVS.

PE4 Priority Encoder Base priority-encoder block verified through schematic simulation and extracted layout validation.

4:1 MUX Structured MUX design using hierarchical 2:1 modules, used to scale the encoder hierarchy into PE16.

PE16 Optimized Design Final scaled encoder optimized through critical-path identification and logic-level reduction — 96.5% delay improvement.

Design Flow

Schematic to Optimized Verified Layout

PE4 Design

Started with a 4-input priority encoder, verified functionality through simulation, calculated load capacitance, and measured worst-case delay across all input vectors.

MUX4 Design

Built a hierarchical 4:1 MUX using 2:1 MUX modules, then expanded into 2-bit and 4-bit MUX structures for integration with the PE16 hierarchy.

PE16 Scaling

Combined PE4 and MUX structures to build a PE16 priority encoder and tested it using vector-based simulations across all 16-input combinations.

Critical Path Optimization

Identified the PE16 worst-case critical path in the fork-like logic structure and improved delay by reducing logic levels — achieving 23.262 ps rise and 24.511 ps fall from an original 707.458 ps fall.

Layout Verification

Created standard cell layouts (INV, AOI21, NOR2, NOR3), built PE4, MUX4, and PE16 floorplans, then validated all with DRC, LVS, extracted simulation, and timing measurements.

Evidence Gallery

Design Documentation

Base 4-input priority encoder module used as the hierarchical building block.

Hierarchical MUX structure used to route encoder outputs into the PE16 system.

Original PE16 architecture combining 4× PE4 and MUX stages.

Optimized PE16 with reduced logic levels after critical-path analysis.

4-input priority encoder full schematic with all logic gates.

Base 2-to-1 multiplexer cell schematic used to build the 4:1 hierarchy.

Single-bit 4:1 MUX schematic built from 2:1 modules.

2-bit output 4:1 MUX schematic for encoder output selection.

Full 4-bit output MUX schematic for PE16 integration.

Complete 16-input priority encoder schematic with PE4 and MUX hierarchy.

Verifies correct priority encoding output across all 4-input combinations.

Confirms MUX output selection for all select-line combinations.

End-to-end PE16 waveform showing correct encoded output before optimization.

Waveform confirming correct output after logic-level reduction optimization.

Post-layout extracted simulation waveforms for PE4, MUX4, and PE16.

Identified worst-case delay path through the PE4 logic structure.

Critical path analysis of the MUX select-to-output timing.

Fork-structure critical path identified at 707.458 ps falling delay.

PE4 logic restructured to reduce the number of cascaded logic levels.

MUX structure updated to align with optimized PE16 hierarchy.

Optimized PE16 achieving 23.262 ps rise / 24.511 ps fall after restructuring.

Side-by-side timing comparison: 707.458 ps fall → 24.511 ps fall (96.5% reduction).

Custom inverter cell layout used as standard cell in all blocks.

AND-OR-INVERT cell layout for the encoder logic implementation.

2-input NOR gate layout used in PE4 and MUX structures.

3-input NOR gate layout for wider encoder logic paths.

Physical layout of the 4-input priority encoder with standard cell placement.

Physical floorplan and layout of the 4:1 MUX block.

Complete PE16 top-level layout with all PE4 and MUX4 blocks placed and routed.

DRC Passed LVS Passed

DRC Passed LVS Passed — Full system clean.

Block	Metric	Value	Notes
PE4	Worst-case delay	—	Schematic-level measurement
MUX4	Worst-case delay	—	Schematic-level measurement
PE16 (original)	Falling delay	707.458 ps	Before optimization
PE16 (optimized)	Rising delay	23.262 ps	After logic-level reduction
PE16 (optimized)	Falling delay	24.511 ps	96.5% reduction from original
PE4	Extracted delay	—	Post-layout extracted simulation
MUX4	Extracted delay	—	Post-layout extracted simulation
PE16	Extracted delay	—	Post-layout extracted simulation

Final Outcome

Project Summary

This project strengthened Mallika's ability to design digital VLSI circuits with performance in mind. She moved from PE4 and MUX schematic construction into PE16 system scaling, identified critical paths, optimized the logic structure to reduce delay by 96.5% (707 ps → 24.5 ps), and completed extracted-layout validation through floorplanning, DRC, LVS, and waveform-based timing analysis.

MallikaShingari

Transistors toTapeout.

Focus Area

Tools & Software

Education

Currently Seeking

Hardware Design Work

Custom Arithmetic Datapath for ASIC-Style Compute Systems

CMOS Logic Cell Design for Arithmetic Circuits

Priority Encoder Optimization for High-Speed Digital Logic

Let's Connect

Custom MOS VLSI Arithmetic Processing Unit

Results Snapshot

Mallika's Focus

Components Owned

From Cells to Verified Silicon

CMOS Cells

Multiplier / Divider Datapath

Arbiter FSM

Layout Verification

Final Performance Metrics

Design Documentation

Project Summary

CMOS Logic Cell Design for Arithmetic Circuits

Results Snapshot

Mallika's Focus

Components Owned

XOR Gate to Verified 4-bit Adder

XOR Gate

Full Adder

DUT Delay Testing

4-bit Ripple-Carry Adder

Layout Verification

Design Documentation

Project Summary

Priority Encoder Optimization for High-Speed Digital Logic

Results Snapshot

Mallika's Focus

Components Owned

Schematic to Optimized Verified Layout

PE4 Design

MUX4 Design

PE16 Scaling

Critical Path Optimization

Layout Verification

Design Documentation

Project Summary

Mallika
Shingari

Transistors to
Tapeout.